| 摘要 |
PROBLEM TO BE SOLVED: To provide an efficient cache prefetch mechanism. SOLUTION: An instruction executing unit 1 reads a prefetch instruction from an instruction cache 2 and a prefetch object address is reported to a precfetch mechanism 6 and a data cache 3. In the case of a cache hit, the prefetch mechanism 6 and the data cache 3 do not execute anything to end instruction processing. In the case of a cache error, the prefetch object address is temporarily stored in the prefetch mechanism 6 and the prefetch mechanism 6 reads data from an external memory through a bus interface 5 and stores the data in the data cache 3 independently of the operation of the instruction executing unit 1. The instruction executing unit 1 only sends the prefetch address to the prefetch mechanism to end processing of cache prefetch, then processing of the next instruction is started.
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