发明名称 DATA TRANSFER CONTROLLER, INFORMATION STORAGE MEDIUM AND ELECTRONIC EQUIPMENT
摘要 PROBLEM TO BE SOLVED: To provide a data transfer controller capable of eliminating deficiency generated at a time when a reset clearing the topology information of a node takes place, an information storage medium and electronic equipment. SOLUTION: When a bus reset occurs in the data transfer controller of an IEEE 1394 standard, the first address of transfer data by an ORB before the bus reset is compared with the first address of transfer data by the ORB after the bus reset, the first addresses are the same, data transfer is restarted by continuing from the point of time when the bus reset takes place to prevent a printer from performing double printing. An address existing at the first segment of a page table is stored in an area different from a page table storage area. ORB contents are compared before comparing the first address. Identification information included by the ORB before and after the bus reset is compared, and when the identification information is the same, data transfer is restarted by continuing from the point of time when the bus reset takes place. When an ACK is not returned from an initiator due to the bus reset, whether or not the initiator receives a completion status is judged on the basis of the identification information of the ORB.
申请公布号 JP2001177536(A) 申请公布日期 2001.06.29
申请号 JP19990361102 申请日期 1999.12.20
申请人 SEIKO EPSON CORP 发明人 MATSUNAGA KOSUKE;KANAI HIROYUKI;FUJITA SHINICHIRO
分类号 B41J29/38;B41J5/30;G06F3/12;G06F13/00;G06F13/12;H04L12/28;H04L29/08;(IPC1-7):H04L12/28 主分类号 B41J29/38
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