| 摘要 |
PURPOSE: To provide a semiconductor memory capable of easilily dealing with the extension of banks without increasing chip area and realizing high speed access. CONSTITUTION: A central row system control circuit 1 transmits an internal row address signal RA < 8:0 > in common to each memory sub-block MSB a common bank of memory mats NM1, NM2 asynchronously with an external clock signal, also, latches a block selecting signal BS < 7:0 > specifying a memory sub-block synchronizing with an internal clock signal CLKR, and transmits it to each memory sub-block. Also, a spare discriminating circuit 4 performs spare discrimination asynchronously with a clock signal.
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