| 摘要 |
<p>When a base register value, an index register value, and a displacement value are given in the case of an operand access, these values are inputted into an arithmetic unit to produce a correctly calculated logical address. A logical address predicting unit predicts a logical address. An absolute address is predicted based on the predicted logical address by using an absolute address history table. An access to a cache memory (LB) on the basis of absolute address is made using the predicted absolute address to acquire cache data. The arithmetic unit calculates the correct absolute address from the correctly calculated logical address by using a TLB and performs coincidence check if the correct absolute address coincides with the predicted absolute address so as to perform result assurance of the cache data read from the LBS. In the case of instruction fetch, similar processings are carried out except that the calculation of logical address is not performed.</p> |
