发明名称 |
Semiconductor device having multilevel interconnection structure and method for fabricating the same |
摘要 |
A method for fabricating a semiconductor device having a multilevel interconnection structure according to the present invention includes the steps of: covering a surface of a substrate with an insulating film; depositing a conductive film on the insulating film; forming a first interlevel dielectric film on the conductive film; forming an interlevel contact hole in the first interlevel dielectric film so as to reach the conductive film; filling in the interlevel contact hole with an interconnecting metal; forming a masking layer, defining a pattern of a first interconnect layer, on the first interlevel dielectric film so as to cover at least part of the interconnecting metal; forming the first interconnect layer out of the conductive film by etching the first interlevel dielectric film using the masking layer as a mask and by etching the conductive film using the masking layer and the interconnecting metal as a mask; removing the masking layer; depositing a second interlevel dielectric film over the substrate so as to cover the interconnecting metal and the first interconnect layer; planarizing the second interlevel dielectric film, thereby exposing at least part of the interconnecting metal; and forming a second interconnect layer to be electrically connected to an upper part of the interconnecting metal.
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申请公布号 |
US6242336(B1) |
申请公布日期 |
2001.06.05 |
申请号 |
US19980186067 |
申请日期 |
1998.11.05 |
申请人 |
MATSUSHITA ELECTRONICS CORPORATION |
发明人 |
UEDA TETSUYA;TAMAOKA EIJI;AOI NOBUO |
分类号 |
H01L21/60;H01L21/768;H01L23/522;(IPC1-7):H01L21/476 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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