发明名称 |
DELAY GENERATOR |
摘要 |
<p>PROBLEM TO BE SOLVED: To provide an output clock obtained by delaying an input clock by desired time with a small circuit scale. SOLUTION: In a voltage comparator 11, the charge voltage Vt of a capacitor C11 is compared with the charge voltage Vr of a capacitor C21 at the first clock of an input clock. The charge voltage Vt of a capacitor C12 is compared with the charge voltage Vr of a capacitor C22 at the second clock. The charge voltage Vt of a capacitor C13 is compared with the charge voltage Vr of a capacitor C23 at the third clock. The charge voltage Vt of the capacitor C11 is compared with the charge voltage Vr of the capacitor C21 at the fourth clock. Then, comparison is repeated and a clock obtained by delaying the input clock is obtained from the voltage comparator.</p> |
申请公布号 |
JP2001148624(A) |
申请公布日期 |
2001.05.29 |
申请号 |
JP19990329687 |
申请日期 |
1999.11.19 |
申请人 |
NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
YAMAGUCHI AKIRA;NOSAKA HIDEYUKI;MURAGUCHI MASAHIRO;YAMAGISHI AKIHIRO |
分类号 |
H03K5/13;(IPC1-7):H03K5/13 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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