| 摘要 |
<p>A memory cell having a floating gate is formed on a semiconductor substrate of a first conduction type and is disposed in a region having a deep well of a second conduction type formed to a semiconductor substrate and a shallow well of a first conduction type formed in the deep well. An erasing operation of emitting electrons from floating gates is conducted utilizing a tunneling phenomenon by setting a control gate terminal to ground voltage and a source terminal S to VPP. The deep and shallow wells are supplied with VCC at time t1 and a source terminal is supplied with VPP at time t2 after a predetermined period of time from time t1 has elapsed.</p> |
