| 摘要 |
A single-instruction multiple-data (SIMD) array processor (100) providing enhanced data transfer efficiency. The SIMD array processor includes at least one memory (102) such as a synchronous dynamic random access memory and a plurality of processing elements (104-134) configured in an array. Each processing element includes at least one "narrow" memory buffer and a plurality of "wide" data registers. The narrow memory buffer transfers data between the memory and at least one of the wide data registers while the processing element performs data processing operations. Each processing element further includes at least one parallel adder for adding data stored in the wide data registers coupled thereto, and a control circuit for controlling the memory buffer to transfer a data word stored in a selected data register between the memory and the selected data register.
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