CLOCK PULSE AND DATA REGENERATOR FOR DIFFERENT DATA RATES

摘要

Figure 1 shows the main block diagram of the inventive regenerator, which ha s a frequency control unit and a phase control unit. The phase control circuit (PLL) consists of a phase discriminator (PD), a loop filter, a controllable oscillator (5) and a frequency divider (6). Said frequency divider forms a clock pulse signal (TS) which is coupled back to a second input of the phase discriminator (PD). The data signal (DSF) is used as a reference signal. The aim of the invention is to provide a clock pulse and data regenerator that functions reliably and contiguously with different data signal bit rates. Th e regenerator should also be improved in such a way that differently coded dat a signals can be processed.