发明名称 TIMING CHECK DEVICE FOR CONTROL SIGNAL OF ARITHMETIC MEANS
摘要 PURPOSE: To fast and easily perform the timing check regardless of the number of commands or the number of patterns changing for each command by providing a parity check means which decides whether the operation timings of control signals of plural types have errors or not. CONSTITUTION: A parity generator 20 is connected to the connection wiring parts 11-1, 11-2, 11-3 and 11-4 which are branched out from an output signal wiring 3 and corresponding to the signals RAS, CAS, WE and CS respectively. Then the generator 20 generates the parities based on the change of each timing of those parts 11-1 to 11-4 and temporarily stores these parities in a parity storage part 21. Then the parities are inputted to a parity checker 22. The parities outputted from the generator 20 are compared with the operation timings of control signals of several types right before they are inputted to a RAM 12. Thus it is decided whether the operation timings of control signals have errors or not.
申请公布号 JPH08106397(A) 申请公布日期 1996.04.23
申请号 JP19940243961 申请日期 1994.10.07
申请人 FUJITSU LTD 发明人 OTSUKI KOJI;NAKANO OSAMU;WAKAYAMA TAKAHIRO;HIRASAWA TSUTOMU;IKEHARA SHOHEI
分类号 G06F11/30;G06F11/00;G06F11/10 主分类号 G06F11/30
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