| 摘要 |
PROBLEM TO BE SOLVED: To reduce a power consumption, to assure driving capability of a scan path necessary for a normal operation and to reduce a simulation time for verifying a test circuit. SOLUTION: The semiconductor integrated circuit comprises a logic circuit having a combinational circuit 11 and a sequential circuit. In this case, outputs D0 to D3 of the circuit 11 are respectively supplied to data input terminals D of flip-flops 12 to 15 of the sequential circuit through multiplexers 22 to 25. The flip-flops 12 to 15 are cascade connected through the multiplexers 23 to 25 to constitute a scan path. The integrated circuit also comprises AND gates 32 to 35 for preventing transmission of a change in outputs of the flip-flops 12 to 15 to the circuit 11 when a scan mode signal *SM is active so that the circuit 11 is not operated when the data are serially transferred through the path. |
