| 摘要 |
<p>In an AFC Automatic Frequency Control circuit, a frequency offset estimating circuit 11 produces a lock signal 102 if a calculated frequency error becomes smaller than a predetermined value. Then, a CPU 13 produces a control signal 104 to stop the operation of the frequency offset estimating circuit 11. A timing generating circuit 14 calculates a frequency error with reference to a frame timing correction amount from a delay profile/search circuit 12 and produces an unlock signal 103 if the frequency error becomes equal to or greater than the predetermined value. Then, the CPU 13 produces the control signal 104 to start the operation of the frequency offset estimating circuit 11. Thus, the frequency offset estimating circuit 11 stops its operation while the AFC operation is in the locked state. In a modification (Fig 5) the frequency offsett estimating circuit 11 is removed and the timing generating circuit 14 determines the lock/ unlock state and a ROM 15 provides an output from the delay profile/search circuit 12 to an accumulator 9.</p> |
