PROCESSOR HAVING CACHE PURGE CONTROL MECHANISM

摘要

PROBLEM TO BE SOLVED: To prevent a malfunction caused at the time of mode switching at a high speed in a processor changing information to be decoded according to a mode. SOLUTION: This processor is provided with a circuit 13 which refers to decoded results or issued results when a write operation is performed to a register 11 including a bit showing the current mode and outputs a purge signal at the time when it is a mode switching signal. When the mode switching signal is written to the register in this way, the purge signal is outputted to the cache 2. Then, the valid of prefetched cache data is turned off to prevent the prefetched data from being decoded in a different mode so that an operation after switching the modes can normally be performed. It is also possible to detect the change of a bit showing a mode and to output a purge signal.