发明名称 |
A METHOD AND A DEVICE FOR TESTING A MEMORY ARRAY IN WHICH FAULT RESPONSE IS COMPRESED |
摘要 |
A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row- and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.
|
申请公布号 |
WO0108161(A3) |
申请公布日期 |
2001.03.22 |
申请号 |
WO2000EP06815 |
申请日期 |
2000.07.17 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
MARINISSEN, ERIK, J.;LOUSBERG, GUILLAUME, E., A.;WIELAGE, PAUL |
分类号 |
G01R31/28;G11C11/401;G11C11/413;G11C29/00;G11C29/02;G11C29/12;G11C29/40;G11C29/44;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|