发明名称 INSULATED-GATE FIELD-EFFECT TRANSISTOR AND MANUFACTURE THEREOF
摘要 PROBLEM TO BE SOLVED: To relax a field concentration by a depletion layer in a drain offset region and to contrive an increase in the breakdown voltage of an insulated-gate field-effect transistor, by a method wherein a high-concentration drain region is formed in such a way that the drain region is encircled by a low-concentration offset region. SOLUTION: A gate insulating film 3 and a gate electrode 4 are extended from a drain offset region 6 to the upper surface of one part of a drain region 7 to correspond to the microscopic formation and the speedup of an element due to an extreme reduction in the width of a gate. The part, which is provided on the side of a channel region 10, of the high-concentration drain region 7 is formed in succession to the region 6, but the region 6 is extended to the part of the outside of the region 7 positioned in the direction intersecting orthogonally the direction of the region 10, and the region 7 is not formed at the part of the outside. Accordingly, the edge of the region 7 positioned on the side of the gate, does never come into contact with the film 3 and a field insulating film, a field concentration in the edge is relaxed and an increase in the breakdown voltage of an insulated-gate field-effect transistor can be realized.
申请公布号 JP2001068676(A) 申请公布日期 2001.03.16
申请号 JP19990236820 申请日期 1999.08.24
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 MATSUMOTO SATOSHI;SAKAI TATSURO
分类号 H01L29/786;H01L21/336;(IPC1-7):H01L29/786 主分类号 H01L29/786
代理机构 代理人
主权项
地址