| 摘要 |
PROBLEM TO BE SOLVED: To output a clock modulated equally with a base clock on average by correcting the delay time of a delay unit and switching the on/off of a delay element for each element and/or group. SOLUTION: In a first cycle C1, the same number of delay elements are used inside delay units D1-D4 and a clock CL is delayed. In the delay unit D4, the clock is delayed longer than a complete 1/2 cycle and inside the delay units D1-D4, the same number of delay elements are cut off. During precise calibration, the delay element of the delay unit is turned on or off and it is continued until the clock is delayed longer than 1/2 cycle in the delay unit D4 in a final stage Cn-1. Since the delay element is turned off in the final stage Cn, the sequence of delay units is corrected and inside the delay unit D4, the clock is reduced to a time shorter than a delay time caused by the delay element that is, shorter than 1/2 cycle of the clock. |
