SYNCHRONOUS MEMORY CONTROL CIRCUIT

摘要

The invention concerns a circuit comprising means (8) for translating first control signals (RW/, RAS/, CAS/) coming from a digital processing system (1) into second control signals (CS/, RAS/, CAS/, RW/, BS, A10, DQM) synchronised on active fronts of a clock signal (CLK) and addressed to the synchronous memory. The translation means include logic means for receiving the first control signals in the form of non-synchronised control signals produced by an asynchronous memory controller of the digital processing system, and for carrying out the translation thereof into second synchronised control signals.