发明名称 Method and device for test vector analysis
摘要 A method and device for testing and manufacturing integrated circuits such as microprocessors, memories, ASICs, programmable logic, and other types of integrated circuits. A test system is designed to test the relevant integrated circuit. A device under test emulator responds to the test system. If modifications are needed, the test system can be modified, and used to test actual devices.
申请公布号 US6197605(B1) 申请公布日期 2001.03.06
申请号 US19990321070 申请日期 1999.05.27
申请人 ALTERA CORPORATION 发明人 SIMUNIC TAJANA;MEHTA NARESH U.;CROME CALEB
分类号 G01R31/3183;G06F17/50;(IPC1-7):H01L21/66 主分类号 G01R31/3183
代理机构 代理人
主权项
地址