| 摘要 |
PROBLEM TO BE SOLVED: To attain a fast operation of an N-multiple PLL circuit by detecting a lock-up state of the circuit and canceling a reset signal at a high speed. SOLUTION: This N-multiple PLL circuit comprises a counter 104 which operates with an input clock, a counter 105 which operates with the clock obtained by reducing the N-multiple clock down to 1/N, a comparator 106 which compares values of counters 104 and 105 with each other and a circuit 107 which controls resetting of the PLL circuit. The value of both counters are equal to each other when the PLL circuit is locked. The PLL circuit detects its lock-up state according to the value of both counters and controls its resetting. In such a constitution, the PLL circuit can fast operate and never operates in its unstable state.
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