| 摘要 |
There is provided a vertical timing signal generating circuit which can operate stably irrespective of the phase relationship between a vertical synchronous signal and a vertical timing signal generated by a counter, and can provide a vertical timing signal having a desired phase. Delay circuit 100 receives vertical synchronous signal Pc 123, outputs as a reset signal a signal which is delayed in phase with respect to input vertical synchronous signal Pc 123 by a predetermined phase, and vertical counter 103 receives horizontal synchronous signal Pb 121 and reset signal Pe 125 outputted from delay circuit 100 and resets the count by using reset signal Pe 125 to count a predetermined number of horizontal synchronous signals 121, thereafter outputting vertical timing signal Pd 127.
|
