METHOD AND SYSTEM FOR MAINTAINING CACHE COHERENCY FOR WRITE-THROUGH-STORE OPERATION IN MULTIPROCESSOR SYSTEM

摘要

PURPOSE: An improved method is provided for maintaining cache coherency by snooping a cache, which is not interposed between a processor and a system bus, while using the data address of write-through-store operation. CONSTITUTION: A processor core performs the bus arbitration of a local bus for transmitting the address of write-through-store operation to the cache of a low-order level (152). The address is compared with the tag arrangement in the cache of the low-order level (154). From the compared result, the presence/absence of hit in the cache of the low-order level is investigated (156). The write-through-store operation is dispatched to the system bus (160). The address is snooped in a non-passing cache (164). The presence/absence of a retry response from the snoop is investigated (168) and when the snoop does not return retry, the system bus is released (172).