发明名称 PROCESSOR
摘要 PROBLEM TO BE SOLVED: To effectively make use of various resources and to perform the out-of-order execution of more instructions by allowing a following instruction which does not depend upon the execution result of a synchronous instruction to perform out-of-order execution by itself as long as it is not a synchronous instruction. SOLUTION: A synchronous instruction detecting decoder 102 judges whether or not an instruction code that a processor 100 reads out of an external memory, etc., is a synchronous instruction which can not be executed before precedent instructions are all executed. Then an S bit of a reorder buffer 103 and an S bit of a reservation station 104 are set for a synchronous instruction and reset for a nonsynchronous instruction. The reservation station 104 feed instructions for which the S bit is not set, i.e., nonsynchronous instructions to a computing element 105 in order instructions which can be operated irrelevantly to the instruction order and executes them. For instructions after operation, an E bit of the reorder buffer 103 is set and the bit of the reservation station 104 is reset.
申请公布号 JP2001051846(A) 申请公布日期 2001.02.23
申请号 JP19990228245 申请日期 1999.08.12
申请人 HITACHI LTD 发明人 KIMURA ISAO;TANAKA KAZUNARI;SHIMADA KENTARO
分类号 G06F9/38;(IPC1-7):G06F9/38 主分类号 G06F9/38
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