发明名称 OPTICAL RECEIVING CIRCUIT AND ITS METHOD
摘要 PROBLEM TO BE SOLVED: To provide an optical receiving circuit and its method which can securely detect a light signal break and can detect a light input break even by using a PLL even if a clock freely runs. SOLUTION: This optical receiving circuit has an avalanche photodiode(APD) 1, an AGC amplifying circuit 2, a peak detecting circuit(DET) 3, a differential amplifier circuit 4, a discriminating circuit 5, a clock extracting circuit 6, an edge detection type phase comparing circuit 7, a selecting circuit(SEL) 8, and a DC/DC converter 9. The clock extracted by the clock extracting circuit 6 has its frequency divided to detect an edge of the clock and the phases of the frequency-divided clock and a reference clock are compared with each other to decide whether or not the light signal has an input break from whether or not both the clock are in phase with each other. This circuit and method are applicable even when a PLL is used as the clock extracting circuit.
申请公布号 JP2001053689(A) 申请公布日期 2001.02.23
申请号 JP19990226982 申请日期 1999.08.10
申请人 NEC MIYAGI LTD 发明人 ITABASHI SHUNICHI
分类号 H01L31/107;H03D13/00;H03K5/1532;H03K5/26;H04B10/079;H04B10/40;H04B10/50;H04B10/524;H04B10/564;H04B10/60;H04B10/67;H04B10/69;H04L7/02 主分类号 H01L31/107
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