摘要 |
In a parallel Analog-to-Digital Converter (ADC) device a number of ADCS work in parallel, the conversion processes in each ADC overlapping the processes in the other ADCs. The number of ADCs and the sampling period at which samples arc taken and new conversion processes are periodically started in the ADCs are selected so that at each instant, at least one ADC is idling not performing any conversion. After the conversion is made by one of the ADCs, a choice is made whether the next sampled value is to be converted by this ADC or by the idling ADC. This choice can be made in a random or a pseudo-random way. Undesired tones existing in the composite output signal of parallel ADC devices having no such extra ADC are transferred to noise, as the error in the output signal caused by differences in the conversion characteristics of the ADCs is distributed in the frequency domain. |