| 摘要 |
A parallel M-sequence generator is disclosed which outputs an identical bit stream of a serial M-sequence generator of equal chip length. In a parallel N-bit implementation, the first N bits of the sequence are read at the output, the remaining bits are shifted, and the new N bits are generated, all in one clock cycle. The effect of obtaining N bits at the output is to multiply the present contents of the shift register by a companion matrix of the Nth order. Linear combining elements (e.g. XOR gates) are selectively positioned to combine the contents of various delay elements of the parallel structure and feedback the results to other delay elements in order to produce the identical output of the serial structure.
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