| 摘要 |
An arrangement for generating test signals for testing a number of semiconductor chips (2-10) in which the test signals (address, DQ) can be supplied to the semiconductor chips in a precise time-relationship to a clock signal. The time sequence of the test signals (address, DQ) at the respective semiconductor chip (2-10) can be determined from the clock signal. The clock signal can be specifically supplied to a DLL-(delay locked loop) unit (19) which generates a delayed clock signal (clockd) from the clock signal which activates a latch (15) connected in series, on the load side, to each signal input of each test signal (address, DQ). A switch (14) is specifically provided parallel to the latch (15), and is controlled by a test- mode signal.
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