| 摘要 |
A memory system and method that allow more than one cycle of memory latency for accesses to a synchronously accessed memory. The memory system includes a memory with a clocked interface and a corresponding clock input, and may include an output register for storing data outputted from the memory during a read operation. The output register and the memory are coupled together by a data path, for transferring data between the memory and the output register. The memory system may further include a clock signal coupled to the clocked interface of the memory. The clock signal feeds through a delay element into a clock input of the output register. This causes the output register to receive a delayed clock signal, thereby providing more than one clock cycle of time for data to be read from the memory and latched in the output register. The memory system may also include an input register, for inputting data during write operations. This input register similarly receives a delayed clock signal, which functions as an advanced clock signal from the preceding clock cycle to provide more than one clock cycle of latency for write accesses to memory. A delay element may be selectively configured to produce variable delay or latency to allow the memory system to flexibly operate with different memory devices and/or processor clock speeds.
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