发明名称 |
Clock synchronizing circuit |
摘要 |
A clock synchronizing circuit provides reduced power consumption. A first phase comparator compares an external clock signal delayed for a predertermined time with a feedback clock signal to detect their phase error, and a second phase comparator compares an external clock signal with a feedback clock signal delayed for a predetermined time to detect their phase error. A charge pump changes a charge amount depending on phase error detecting signals from the first and second phase error comparators, and a phase compensator compensates the phase of the external clock signal depending on the charge amount from the charge pump. A controller controls the overall system or some portion thereof to be converted to a power save mode if the phase of the external clock signal is synchronized with that of the feedback clock signal by the phase compensator.
|
申请公布号 |
US6184733(B1) |
申请公布日期 |
2001.02.06 |
申请号 |
US19990453479 |
申请日期 |
1999.12.02 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
WANG SUNG HO;JUN YOUNG-HYUN |
分类号 |
G06F1/12;H03K19/00;H03L7/08;H03L7/081;H03L7/087;H04L25/40;(IPC1-7):H03L7/06 |
主分类号 |
G06F1/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|