发明名称 |
Method to form bottom electrode of capacitor |
摘要 |
A method for fabricating a bottom electrode is provided. In this method a dielectric layer is formed on a substrate having a source/drain region. A via hole is formed in the dielectric layer to expose the source/drain region. A patterned, doped polysilicon layer is formed on the dielectric layer and fills the via hole, wherein the cross-section of the patterned doped polysilicon layer is arced or polygonal. The surface of the patterned polysilicon layer is transformed into an amorphous silicon layer. A hemispherical-grain layer is formed on the amorphous silicon layer.
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申请公布号 |
US6177326(B1) |
申请公布日期 |
2001.01.23 |
申请号 |
US19980208607 |
申请日期 |
1998.12.08 |
申请人 |
UNITED MICROELECTRONICS CORP. |
发明人 |
WU YI-TYNG;LIN KUO-CHI |
分类号 |
H01L21/02;(IPC1-7):H01L21/20 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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