发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS INSPECTING METHOD |
摘要 |
PROBLEM TO BE SOLVED: To efficiently inspect signal transmission paths connecting an inspection signal creation point to an inspection signal observation point and to inspect delay failures in a larger number of signal transmission paths by a smaller number of inspecting circuits in a method for inspecting semiconductor integrated circuits. SOLUTION: In a semiconductor integrated circuit to which an inspecting circuit 100 is mounted, a predetermined signal transmission path to be an object of inspection is selected from among a plurality of signal transmission paths in a logic circuit 100a which constitutes the inspecting circuit 100. Then an inspection clock with a cycle according to a design delay time corresponding to the selected signal transmission path is outputted from an inspection timing creating part 210 to a register (inspection signal creation point) 201 and registers (inspection signal observation points) 202 and 203, and an inspection signal is created and observed at each register.
|
申请公布号 |
JP2001013220(A) |
申请公布日期 |
2001.01.19 |
申请号 |
JP20000126511 |
申请日期 |
2000.04.26 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
OTA MITSUHO;HOSOKAWA TOSHINORI;TAKEOKA SADAMI;ICHIKAWA OSAMU |
分类号 |
G01R31/28;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|