| 摘要 |
PROBLEM TO BE SOLVED: To effectively utilize a protective circuit for another use by providing an excellent ESD(electrostatic discharge) durability with a simple protective circuit configuration. SOLUTION: An internal circuit 2 is formed in a semiconductor chip 1, and an NMOS protective transistor QN is connected to a signal line 3 between the internal circuit 2 and a pad PAD. The gate of the transistor QN is connected to the output terminal of a logic gate 4. The logic gate 4 is activated by a test mode selecting signal TM so that the output of a test circuit 21 is transferred to the gate of the protective transistor QN. When no power source is supplied, the gate of the protective transistor QN is floating by the logic gate 4, showing a high ESD durability. At normal operation, the protective transistor QN maintains an off state. In a test mode, the protective transistor QN is driven depending on the output of the test circuit 21, acting as an output circuit.
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