| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a power line layout in which the influence of power line noise can be effectively reduced. SOLUTION: A silicon substrate 1 is divided into an NMOS transistor region 3 and a PMOS transistor region 4, and signal lines 6 and 8 are formed of metal layers M1 and M2 in each of the regions 3 and 4. A VSS line (low-level side power line) 10 and a VDD line (high-level side power line) 14, each having the same width, overlap each other in the upper part of the region 3, whereas a VDD line 11 and VSS line 13, each also having the same width, overlap in the upper part of the region 4. The lines 10 and 11 are formed by patterning the same layer M3, whereas the lines 13 and 14 are formed by patterning the same layer M4. A MOS capacitor C is connected between two adjacent ones of the lines 10, 11, 13 and 14.
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