METHOD OF COMPENSATING FOR MATERIAL LOSS IN A METAL SILICIDE LAYER IN CONTACTS OF INTEGRATED CIRCUIT DEVICES

摘要

There is provided a semiconductor device comprising, for example, an MOS structure (101) having a low electrical resistance in contacts and local interconnects, and a method for fabricating the device. When openings (102) are formed in a dielectric region (119) of an MOS structure (101), the thin metal silicide layer (109) on top of a drain/source region (103) is diminished due to the limited selectivity of the etch process and the need to over-etch to obtain appropriate electrical contacts. Consequently, the contact resistance is increased resulting in an increased contact resistance. Therefore, a bilayer metal (115) is deposited on the metal silicide layer (109) and the surface of the openings, wherein the metal layer that is in contact with the metal silicide layer (109) is preferably the same metal as the metal of the metal silicide layer. In a subsequent annealing process, the metal of the bilayer partially converts into metal silicide, thereby increasing the initial metal silicide layer and concurrently reducing the contact resistance.