| 摘要 |
PURPOSE: A wafer level package is provided to be capable of increasing the capacitance while reducing the resistance, by distributing a metal layer for power all over an insulating layer and thus significantly expanding the area of the power. CONSTITUTION: A wafer level package includes a semiconductor chip on which a bonding pad is formed. Insulating layers(61-64) of at least more than three layers are applied on the surface of the semiconductor chip. Metal patterns(90) of at least more than two layers are intervened between the surface of the semiconductor chip and the lowest insulating layer and are also connected to the bonding pad. The metal patterns each are intervened between the insulating layers, respectively and are electrically connected to each other. A junction assistance layer is formed at the metal pattern portion exposed through the top insulating layer. A solder ball is mounted on the junction assistance layer.
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