A system for allowing a central processing unit to access a plurality of interrupt handler routines and a method thereof

摘要

A method and an apparatus for allowing a central processing unit to access a plurality of interrupt handler routines and especially for allowing an embedded microcomputer to handle multiple interrupt request in a fast and an efficient manner. The method and apparatus involve the generation of an selected address, which pointer either to a selected interrupt vector or to a selected interrupt request handler routine. The interrupt vector stores a branch instruction to the selected interrupt request handler. <IMAGE>