Method and apparatus for sampling multiple potentially concurrent instructions in a processor pipeline
摘要
An apparatus is provided for sampling multiple concurretly executing instructions in a processor pipeline of a system. The pipeline has a plurality of processing stages. The apparatus identifies multiple selected when the instructions are fetched into a first stage of the pipeline. A subset of the the multiple selected instructions to execute concurrently in the pipeline. State information of the system is sampled while any of the multiple selected instructions are in any stage of the pipeline. Software is informed whenever all of the selected instructions leave the pipeline so that the software can read any of the state information.
申请公布号
US6163840(A)
申请公布日期
2000.12.19
申请号
US19970980168
申请日期
1997.11.26
申请人
COMPAQ COMPUTER CORPORATION
发明人
CHRYSOS, GEORGE Z.;DEAN, JEFFREY;HICKS, JAMES E.;LEIBHOLZ, DANIEL L.;MCLELLAN, EDWARD J.;WALDSPURGER, CARL A.;WEIHL, WILLIAM E.