发明名称 IC testing method
摘要 An IC testing method is disclosed in which IC's to be tested are placed on IC carriers disposed in an m-row, n-column array on a test tray in a loader, and the IC's to be tested are connected to sockets disposed as an m-row, k-column array on a socket attachment in a manner corresponding to every a-th column of the IC carriers in a testing section for purpose of measurement. n and k are integers equal to or greater than two, n=ak where a is an integer equal to or greater than two. The IC testing method comprises the steps of determining if the number of IC's to be tested which are present in the loader is greater than the number of IC carriers, if it is determined that the number of IC's to be tested is equal to or greater than the number of IC carriers, causing the loader to load the IC's to be tested on all the IC carriers on the test tray, and causing the test section to connect the loaded IC's to be tested which are located in k columns corresponding to every a-th column of the IC carriers with the corresponding sockets to perform a test of simultaneous measurement and to repeat the test a times while translating the test tray by an IC carrier array pitch, thus completing the testing of all the IC's to be tested on the test tray. If it is determined that the number of IC's to be tested is less than the number of IC carriers, the IC's to be tested are disposed at respective positions in a sequence of columns which are subject to a simultaneous measurement in the test section, and the IC's to be tested in every a-th column of the IC carriers are connected with the corresponding sockets to perform a test of simultaneous measurement in the test section, and such test is repeated while translating the test tray by an IC carrier array pitch.
申请公布号 US6163146(A) 申请公布日期 2000.12.19
申请号 US19980042802 申请日期 1998.03.17
申请人 ADVANTEST CORPORATION 发明人 SUZUKI, KATUHIKO;ONISHI, TAKESHI;NAKAZAWA, HIDETAKA
分类号 G01R31/26;G01R31/316;H01L21/66;(IPC1-7):G01R31/02 主分类号 G01R31/26
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