Mechanism for decoding linearly-shifted codes to facilitate correection of bit errors due to component failures

摘要

A mechanism for decoding linear shifted codes employs two shift registers. The shift registers are independently controlled by an associated control unit. Initially, the received parity bits are stored in a first shift register and the global syndrome bits are stored in a second shift register. While the right-most cell in the first shift register contains a logical "0", both shift registers are shifted right one position. When the right-most cell of the first shift register contains a "1", the content of the right-most cell of the second shift register is recorded as a first bit of a syndrome code which identifies the position of an error with any groups with an error. If the value recorded is a "1", a bit-wise exclusive OR operation is then performed on the values in the first and second shift registers, and the result is stored in the second shift register. Subsequently, the contents of the second shift register are shifted by one position. Similar to the previous operation, the content of the right-most cell of the second shift register is again recorded, this time as the next bit of the syndrome code. A bit-wise exclusive OR is again conditionally performed upon the values in the first and second shift registers depending upon whether the last recorded bit was a "1" (and the result is stored in the second shift register), and the contents of the second shift register are shifted. These steps are repeated until all L bits of the syndrome code identifying a failed component have been recorded (where L is the smallest integer such that 2L>=M, where M is the number of components used).