发明名称 PHASE LOCK SYSTEM AND METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a phase lock system which generates plural stable synchronous clocks from a fluctuation clock. SOLUTION: A phase lock system of a remote device for inputting a clock signal from a remote clock generation source is equipped with plural frequency synthesizers which follow the clock signal and generate the clock signal of plural frequencies, plural clock generation circuits 2-4 which individually count generated clock signals, initialize them by a specified count value and generate an output clock in a repetition cycle of the count, window circuits 2-5 which hold an upper limit value and a lower limit value for monitoring the count value at every repetition period and individually initialize the count value when the count value reaches the upper limit value and the lower limit value if the monitored count value shifts from a range determined by the upper value and the lower value, and abnormality detection parts 2-2, 2-6 and 2-10 which monitor the clock signal to be inputted to the remote device, generates an initial synchronous pulse when a power source is supplied at the time of abnormality of the monitored clock signal and initialize all the count values simultaneously.
申请公布号 JP2000349744(A) 申请公布日期 2000.12.15
申请号 JP19990155804 申请日期 1999.06.02
申请人 NEC CORP 发明人 NARAHARA NOBORU
分类号 H04L7/033 主分类号 H04L7/033
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