发明名称 |
TIME/DIGITAL CONVERTER, SYNCHRONIZING CIRCUIT AND METHOD USING THE SAME |
摘要 |
PURPOSE: There is provided a synchronizing circuit for minimizing a phase difference between a reference clock signal and an inner clock signal, and a time/digital converter used for minimizing the phase difference. CONSTITUTION: A time/digital converter(211) includes first and second delay chains for delaying one of two input signals by a predetermined time interval. This time/digital converter also has first and second phase comparators for comparing the phase of the delayed signal with that of the other signal to generate a digital signal. A synchronizing loop converts a phase difference between a feedback signal and an inner clock signal into a delay control signal group using the time/digital converter. The delay control signal group controls the amount of delay of a delay reflecting circuit(207) to minimize the phase difference between the feedback signal and the inner clock signal rapidly.
|
申请公布号 |
KR20000075411(A) |
申请公布日期 |
2000.12.15 |
申请号 |
KR19990044298 |
申请日期 |
1999.10.13 |
申请人 |
SAMSUNG ELECTRONICS CO, LTD. |
发明人 |
LEE, DONG YUN;JUNG, GI UK |
分类号 |
G11C11/407;G06F1/08;G06F1/12;G11C7/22;H03K3/356;H03L7/00;H03L7/08;H03L7/081;H03L7/087;H04L7/033;(IPC1-7):H03L7/08 |
主分类号 |
G11C11/407 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|