DELAY LOCK LOOP UNIT

摘要

PROBLEM TO BE SOLVED: To reduce a circuit scale of a delay lock loop unit by employing a multi-value signal for demodulating the signal in the CDMA system, binarizing a received signal and using the binarized signal so as to lock the synchronization thereby simplifying a multiplier and an integrator. SOLUTION: A binarizing circuit 10 converts a base band signal into a binary 1-bit signal, devides the signal into parallel signals the signals are multiplied by a +Tc/2 signal and a -Tc/2 signal outputted from a PN signal generator 11. Since the multiplication is made between 1-bit signals, the multipliers are configured simply as Ex-OR circuits 12a, 12b and up-down counters 13a, 13b integrate the outputs of the Ex-OR circuits 12a, 12b. The up-down counters 13a, 13b conduct up-count when the output of the multiplier is '1' and conduct down-count when the output of the multiplier is '0' so as to make integration for a prescribed time and registers 14a, 14b store outputs of the up-down counters 13a, 13b. A difference between outputs of the registers 14a, 14b is calculated and the difference is given to an LPF 16, which generates a phase adjustment signal. The signal is used to control a VCO 17, which activates the PN generator 11.