发明名称 Semiconductor memory device allowing efficient column selection
摘要 In a memory mat of a semiconductor memory device according to the present invention, a main column select line is provided for every n column addresses and a n sub column select lines are arranged for every main column select line (n is a natural number). In response to a column address signal, a main column select line is selected and a burst circuit and a sub decoder activate a corresponding sub decode signal. A sub column decoder drives a sub column select line according to the states of the main column select line and the sub decode signal.
申请公布号 US6160751(A) 申请公布日期 2000.12.12
申请号 US19990350921 申请日期 1999.07.12
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 TOMISHIMA, SHIGEKI
分类号 G11C11/41;G11C8/10;G11C8/12;G11C11/401;G11C11/407;G11C11/408;(IPC1-7):G11C8/00 主分类号 G11C11/41
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