| 摘要 |
PROBLEM TO BE SOLVED: To correctly read out data and reduce power consumption when the data is read out by forming a drain and a source regions of each memory cell transistor in a column direction of a part of a first and a second bit lines, connecting the memory cell transistor to a discharging means by the second bit line, and bringing the discharging means into an open state when the first bit line is started to be charged by a charging means. SOLUTION: A memory cell array consisting of memory cell transistors M1-M3 has word lines WL1-WLn connected to a gate electrode, and bit lines BIT11, BIT12... and BIT21, BIT22... connected to a drain electrode and a source electrode. Bit lines BIT11, BIT12 and BIT21, BIT22 are connected to a read charge transistor Tr4 and a discharge transistor Tr3 via bit line selection transistors Tr12, Tr11 and Tr21, Tr22 respectively. A charge control signal CKD is applied via a signal CKP and a delay circuit 10 to gate electrodes of the charge transistor Tr4 and discharge transistor Tr3. |
