发明名称 |
ARRAY ARCHITECTURE AND OPERATING METHODS FOR DIGITAL MULTILEVEL NONVOLATILE MEMORY INTEGRATED CIRCUIT SYSTEM |
摘要 |
Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining. |
申请公布号 |
WO0042615(A3) |
申请公布日期 |
2000.11.30 |
申请号 |
WO2000US01077 |
申请日期 |
2000.01.13 |
申请人 |
AGATE SEMICONDUCTOR, INC. |
发明人 |
TRAN, HIEU, VAN;KHAN, SAKHAWAT, M.;KORSH, GEORGE, J. |
分类号 |
G11C11/56;G11C16/08;G11C16/10;G11C16/24;G11C16/28;G11C27/00 |
主分类号 |
G11C11/56 |
代理机构 |
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