| 摘要 |
PROBLEM TO BE SOLVED: To provide a data transmission circuit securing the accurate timing of signal transmitted on a transmission line having different length and propagation speed by including a variable delay circuit that selectively varies a relation between clock signals. SOLUTION: A circuit has a master latch 20, a slave latch 22 and a clock line 24 supplying a clock CK to the latches 20 and 22 and includes a variable delay circuit 26. The circuit 26 includes a NOR gate 28, a multiplexer 30, a code selection register 34 and a plurality of selectable delay elements 32. One of inputs of the multiplexer 30 is selected as an output for being supplied to an inverter 40 under the control of the register 34, and an input having desired delay is selected to be supplied as an input of the latch 20. The clocks of the latches 20 and 22 to each transmission line are controlled, and the data output of the latch 22 are synchronized between the two circuits all the time. |
