| 摘要 |
<p>A signal processing circuit capable of improving an S/N ratio of common mode rejection operation at a low power source voltage. In the signal processing circuit, a voltage difference between first and second signals is amplified by a first amplifier circuit and a second amplifier circuit having characteristics opposite to characteristics of the first amplifier circuit, a signal amplified by the first amplifier circuit is converted into a digital signal by a first converter circuit, a signal amplified by the second amplifier circuit is converted into a digital signal by a second converter circuit, and a differential circuit calculates a difference between an output signal from the first converter circuit and an output signal from the second converter circuit, wherein the first amplifier circuit outputs an amplified signal to the first converter circuit by receiving a voltage corresponding to a lower limit value of the input dynamic range of the first converter circuit, and the second amplifier circuit outputs an amplified signal to the second converter circuit by receiving a voltage corresponding to an upper limit value of the input dynamic range of the second converter circuit. <IMAGE></p> |
