| 摘要 |
<p>The timing characteristics of an integrated-circuit design with an original combination-logic module (10) can be potentially improved by moving an input signal (A) with problematic timing in the original module so that it controls an output multiplexer (25) in a revised module (20). The revised module includes two submodules (21 and 22). The first submodule provides the desired logic result where the late signal is low; the second submodule provides the desired logic result where the late signal is high. The multiplexer is controlled by the late signal so that its output is the desired logic result under steady-state conditions. If there are other input signals requiring timing advancement, the method can be reiterated. The method can be iterated until specifications are met or it is clear that the method cannot meet specifications by additional iterations.</p> |
