| 摘要 |
PROBLEM TO BE SOLVED: To adjust a phase difference between both pulse signals to substantially provide a phase difference of 180 degrees to the two pulse signals even when there is dispersion in a delay amount of each of inverters being component of a variable delay circuit. SOLUTION: The phase adjustment circuit is provided with a variable delay circuit 10 that generates a delayed clock pulse (DCLK) by delaying a clock pulse (CLK) signal and with a delay adjustment circuit 20 that adjusts a delay of the variable delay circuit 10 depending on a result of measurement of a phase difference between the CLK signal and the DCLK signal. The delay adjustment circuit 20 is provided with a PLL circuit 30 having a voltage controlled oscillator 33 consisting of a ring oscillator and having a counter 35 to count number of circulations of the signal in the ring oscillator. A state of the PLL circuit 30 at each of an up-edge time of the CLK signal and an up-edge time of the DCLK signal are compared and number of inverter stages of the variable delay circuit 10 is controlled in response to the result of comparison. |
