| 摘要 |
<p>PROBLEM TO BE SOLVED: To execute packet analysis in real time with a simple constitution by controlling a register so that objective data are included in a packet shown by the register and reading the packet shown by the register from a first storing means into a second storing means. SOLUTION: A register is controlled so as to include objective data in a packet shown by the register and the packet shown by the register is read from a first storing means into a second storing means. In this device, the TS memory control part 31 of a data analyzing part 20 reads a TS block designated by an SEG register 34 from an external memory to store it into a TS[] memory 32 in accordance with the reading instruction of a payload by an operation program. In this case, the register 34 is controlled so that the data of a reading object are included in the TS block shown by the register 34, and the TS block shown by the SEG register 34 is written in the memory 32.</p> |
