发明名称 |
METHOD AND APPARATUS FOR ARITHMETIC OPERATIONS |
摘要 |
<p>It is an object of the present invention to provide an arithmetic logic unit that can perform a sum-of-products operation in a reduced number of processing cycles without carrying out data transfer and additions even in obtaining a single result from a plurality of divided input data words. Data words X and Y are input. A product of the high-order bits of X and Y is calculated using first decoder 511, first selector 521, first partial product generator 531 and first full adder 541. A product of the low-order bits of X and Y is also calculated using second decoder 512, second selector 522, second partial product generator 532 and second full adder 542. These products are adaptively shifted at a shifter 55 and then added up with a fed back data word Z at a third full adder 56 and a carry-propagation adder 58. In this manner, the data word Z, representing the result of the sum-of-products operation, is obtained. <IMAGE></p> |
申请公布号 |
EP1049025(A1) |
申请公布日期 |
2000.11.02 |
申请号 |
EP19990900659 |
申请日期 |
1999.01.21 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KANAKOGI, TOMOCHIKA;NAKAJIMA, MASAITSU |
分类号 |
G06F7/533;G06F7/57;G06F7/52;G06F7/544;(IPC1-7):G06F7/544 |
主分类号 |
G06F7/533 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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